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ION Computer Systems, Inc.
SPEC CPU2000 Flags Description

Intel C/C++/FORTRAN Compilers Version 9.1

Linux
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General Options (C/C++/FORTRAN)
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-fast		This option maximizes speed across the entire program by
		including the following Options

		-O3 -ipo -no-prec-div -static -xP

-O{1|2|3}	Optimization-level options:
		1: optimize for speed, but disable some optimizations which
		   increase code size for a small speed benefit.  Includes
		   inline expansion for intrinsic functions, global
		   optimizations, string pooling optimizations.
		2: This is the default level of optimization.
               Optimizes for speed. The -O2 option includes O1 
		   optimizations and in addition enables inlining of 
		   intrinsics and more speed optimizations.
		3: Builds on -01 and -02 optimizations by enabling high-level 
		   optimization. This level does not guarantee higher performance 
		   unless loop and memory access transformation take place. In 
		   conjunction with -QaxK/-QxK and QaxW/QxW, this switch causes
		   the compiler to perform more aggressive data dependency 
		   analysis than for -O2. This may result in longer compilation 
		   times.

-Oa[-]	Assume [do not assume] no aliasing in program.

-align
		This option tells the compiler to analyze and reorder memory layout for variables 
		and arrays. It sets the alignment for objects of type long long, double, and 
		long double to values more suited to best performance.  If you are not interacting 
		with system libraries or other libraries that are compiled without -align, this option 
		can improve performance by reducing misaligned accesses.


-ansi_alias
		Enable/disable use of ANSI aliasing rules in
		optimizations; user asserts that the program adheres to
		these rules.  The default for C++ is -Qansi_alias-
		which is that aliasing rules are not assumed.  The default for
		the Fortran compiler is -Qansi_alias. For C++, the -Qansi_alias
		flag will enable optimizations that would otherwise be
		prevented by potential aliasing.

-auto_ilp32
		Instructs the compiler to analyze the program to determine if there are 
		64-bit pointers which can be safely shrunk into 32-bit pointers.


-ipo		Multi-file ip optimizations that includes:
		- inline function expansion
		- interprocedural constant propogation
		- dead code elimination
		- propagation of function characteristics
		- passing arguments in registers
		- loop-invariant code motion

-msse3
		Generates code for Intel Pentium 4 processors with Streaming SIMD 
		Extensions 3 (SSE3).


-no-prec-div[-]
		Enables optimizations that give slightly less precise results than full IEEE division.

-prof_gen
		Instrument program for profiling for the first phase of 
		two-phase profile guided optimization.

-prof_use
		Instructs the compiler to produce a profile-optimized 
		executable and merges available dynamic information (.dyn) 
		files into a pgopti.dpi file. If you perform multiple 
		executions of the instrumented program, -Qprof_use merges 
		the dynamic information files again and overwrites the 
		previous pgopti.dpi file.  Without any other options,
		the current directory is searched for .dyn files.

-static
		This option prevents linking with shared libraries. It causes the executable 
		to link all libraries statically.


-x<codes>
		Generate specialized code for processor specified by <codes>
		while also generating generic code.

		<codes> includes one or more of the following:

		K: Intel Pentium III or copmatible Intel processors (SSE)
		W: Intel Pentium 4 and compatible Intel processors (SSE2)
		N: Intel Pentium 4 and compatible Intel processors (SSE2)
		   Enables new optimizations in addition to Intel processor-specific
		   optimizations.
		P: Intel Pentium 4 processors and compatible Intel processors with SSE3
		B  Intel Pentium M and compatible Intel processors (SSE2)

		SSE is Streamng SIMD Extensions

		Additional Notes on <codes> N and P:
		------------------------------------
		The N and P options target your program to run on Intel Pentium 4
		and compatible Intel processors.  The resulting code might
		contain unconditional use of features that are not supported
		on other processors.  Programs, where the function main() is
		compiled with this option, will detect non compatible processors
		and generate an error message during execution.  This option
		also enables new optimizations in addition to Intel processor
		specific optimizations.
		These options also enable advanced data layout and code restructuring
		optimizations to improve memory accesses for Intel processors.		

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Flags Specific to FORTRAN
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-align all	
		Instructs compiler to align data items by adding padding bytes
		wherever possible to obtain the natural alignment of data items
		in common blocks, derived types, and record structures.

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General Options
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+FDO		PASS1=-prof_gen  PASS2=-prof_use

		Using feedback-directed optimization, a profile is generated 
		on the first pass of compilation and used on the second pass.

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Benchmark-Specific Portability Options
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178.galgel: 
   -FI
            Fixed-format F90 source code. 

186.crafty:
   -DLINUX_i386
            Linux Intel system, use "long long" as 64bit variable. 
252.eon:
   -DHAS_ERRLIST 
            Tells that the system provides the "sys_nerr" and "sys_errlist[]" variables

253.perlbmk: 
   -DSPEC_CPU2000_LINUX_I386
            Enable the code changes for porting to Linux on i386 architecture to be utilized
   -DSPEC_CPU2000_NEED_BOOL
            Use SPEC provided definition of the boolean type
   -DSPEC_CPU2000_LP64
            Compile using LP64 programming model. 

254.gap: 
   -DSYS_IS_USG 
            Tells that the operating system is USG compliant
   -DSPEC_CPU2000_LP64
            Compile using LP64 programming model. 

255.vortex:
   -DSPEC_CPU2000_LP64
            Compile using LP64 programming model. 

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BIOS Settings
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Enhanced SpeedStep Disabled in BIOS
		Select "Disabled" for maximum CPU speed. Select "Enabled" to
		allow OS to reduce power consumption. Enabled by default.
Hardware Prefetcher Enabled in BIOS
                Enables a processor mechanism that automatically fetches
                data and instructions into the unified second-level cache.
		Enabling this feature can result in higher performance on 
		some applications and operating systems.  Enabled by default.
Adjacent Cache Line Prefetch Enabled in BIOS
		Enables a processor mechanism to fetch the adjacent cache 
		line within an 128-byte sector that contains the data 
                needed due to a cache line miss.
		Enabling this feature can result in higher performance on 
		some applications and operating systems.  Enabled by default.